1. general description the 74axp2g07 is a dual non-inverting buffer with open-drain outputs. schmitt-trigger action at the inputs makes the ci rcuit tolerant of slower input rise and fall times. this device ensures very low static and dynamic power consumption across the entire v cc range from 0.7 v to 2.75 v. it is fully sp ecified for partial power-down applications using i off . the i off circuitry disables the output, preventing the potentially damaging backflow current through the de vice when it is powered down. 2. features and benefits ? wide supply voltage range from 0.7 v to 2.75 v ? low input capacitance; c i = 0.5 pf (typical) ? low output capacitance; c o = 0.7 pf (typical) ? low dynamic power consumption; c pd = 1.0 pf at v cc = 1.2 v (typical) ? low static power consumption; i cc = 0.6 ? a (85 ? c maximum) ? high noise immunity ? complies with jedec standard: ? jesd8-12a.01 (1.1 v to 1.3 v) ? jesd8-11a.01 (1.4 v to 1.6 v) ? jesd8-7a (1.65 v to 1.95 v) ? jesd8-5a.01 (2.3 v to 2.7 v) ? esd protection: ? hbm ansi/esda/jedec js-001 class 2 exceeds 2 kv ? cdm jesd22-c101e exceeds 1000 v ? latch-up performance exceeds 100 ma per jesd 78 class ii ? inputs accept voltages up to 2.75 v ? low noise overshoot and undershoot < 10 % of v cc ? i off circuitry provides partial power-down mode operation ? multiple package options ? specified from ? 40 ? cto+85 ? c 74axp2g07 low-power dual buffer wi th open-drain output rev. 1 ? 24 september 2014 product data sheet
74axp2g07 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights r eserved. product data sheet rev. 1 ? 24 september 2014 2 of 16 nxp semiconductors 74axp2g07 low-power dual buffer with open-drain output 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram table 1. ordering information type number package temperature range name description version 74axp2g07gm ? 40 ? c to +85 ? c xson6 plastic extremely thin sm all outline package; no leads; 6 terminals; body 1 ? 1.45 ? 0.5 mm sot886 74axp2g07gn ? 40 ? c to +85 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 0.9 ? 1.0 ? 0.35 mm sot1115 74axp2g07gs ? 40 ? c to +85 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 1.0 ? 1.0 ? 0.35 mm sot1202 table 2. marking codes type number marking code [1] 74axp2g07gm r7 74axp2g07gn r7 74axp2g07gs r7 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) p q e $ < $ < $ < p q e $ < p q d $ < * 1 '
74axp2g07 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights r eserved. product data sheet rev. 1 ? 24 september 2014 3 of 16 nxp semiconductors 74axp2g07 low-power dual buffer with open-drain output 6. pinning information 6.1 pinning 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level; z = high-impedance off state. fig 4. pin configuration sot886, sot1115 and sot1202 d d d $ ; 3 * 7 u d q v s d u h q w w r s y l h z $ < * 1 ' 9 & |